ENDPOINT ０

今回は使用しません

ENDPOINT １

今回は使用しません

ENDPOINT ２

OUT (PC　→ EZ-USB FX2)

write PORTB

ENDPOINT 4

今回は使用しません

ENDPOINT ６

 IN  (PC ← EZ-USB FX2)

read PORTA

ENDPOINT ８

今回は使用しません

　赤字は説明です　青字は変更箇所

bulkloop.c

void TD_Init(void)             // Called once at startup

{

   // set the CPU clock to 48MHz (E600)　（　）内はレジスタアドレス

   CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   // set the slave FIFO interface to 48MHz (E601)

//   IFCONFIG |= 0x40;　GPIFやslaveFIFO未使用なのでコメントにしました

  // Registers which require a synchronization delay, see section 15.14

  // FIFORESET        FIFOPINPOLAR

  // INPKTEND         OUTPKTEND

  // EPxBCH:L         REVCTL

  // GPIFTCB3         GPIFTCB2

  // GPIFTCB1         GPIFTCB0

  // EPxFIFOPFH:L     EPxAUTOINLENH:L

  // EPxFIFOCFG       EPxGPIFFLGSEL

  // PINFLAGSxx       EPxFIFOIRQ

  // EPxFIFOIE        GPIFIRQ

  // GPIFIE           GPIFADRH:L

  // UDMACRCH:L       EPxGPIFTRIG

  // GPIFTRIG

  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...

  //      ...these have been replaced by GPIFTC[B3:B0] registers

  // default: all endpoints have their VALID bit set

  // default: TYPE1 = 1 and TYPE0 = 0 --> BULK  

  // default: EP2 and EP4 DIR bits are 0 (OUT direction)

  // default: EP6 and EP8 DIR bits are 1 (IN direction)

  // default: EP2, EP4, EP6, and EP8 are double buffered

  // we are just using the default values, yes this is not necessary...

  // EP0IN & OUT = 64bytes

  // EP1IN = 64bytes

  // EP1OUT = 64bytes

  // EP2+EP4+EP6+EP8 = 4KBytes

  EP1OUTCFG = 0xA0;//Active Endpoint1-out , type = BULK (E610)

  EP1INCFG = 0xA0; //Active Endpoint1-in  , type = BULK (E610)

  SYNCDELAY;       //Read and Write access to E600-E6FF registers

                           // must be separated by a syncdelay

  EP2CFG = 0xA2;   //Active Endpoint2 , dir = out, type = BULK ,

                            // size = 512(Select), buf = size x 2(select) (E612)

  SYNCDELAY;                    

  EP4CFG = 0xA0;   //Active Endpoint4 , dir = out, type = BULK ,

                            // size = 512(fix) ,  buf = size x 2(fix) (E613)

  SYNCDELAY;                    

  EP6CFG = 0xE2;   //Active Endpoint6 , dir = in , type = BULK ,

                            // size = 512(Select), buf = size x 2(select) (E614)

  SYNCDELAY;                    

  EP8CFG = 0xE0;   //Active Endpoint8 , dir = in , type = BULK ,

                            //size = 512(fix) ,  buf = size x 2(fix) (E615)

  // out endpoints do not come up armed

  // since the defaults are double buffered we must write dummy byte counts twice

  SYNCDELAY;                    

  EP2BCL = 0x80;   // arm EP2OUT by writing byte count w/skip. (E691)

  SYNCDELAY;                    

  EP2BCL = 0x80;

  SYNCDELAY;                    

  EP4BCL = 0x80;   // arm EP4OUT by writing byte count w/skip. (E695)

  SYNCDELAY;                    

  EP4BCL = 0x80;    

  // enable dual autopointer feature

//  AUTOPTRSETUP |= 0x01;// Then, for every read and write of an

　　　　　　//  AUTOPTRHn/Ln register, the address pointer auto increments (AF)

　　　AUTOPTRHn/Ln等のオートポインタは未使用なのでコメントにしました

}

void TD_Poll(void)

{

   WORD send_count;

   OEB = 0xff;//PORTB all Output bit  PORTBを出力に設定

  //EP2 is OUT (Host->Device) , write PORTB

  //EP6 is IN  (Device->Host) , read PORTA

  if(!(EP2468STAT & bmEP2EMPTY))　EP2が空でないとき（ホストからデータ有り）

  { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR),

    // core set's this bit when FIFO is empty

     if(!(EP2468STAT & bmEP6FULL))　EP６が一杯でないとき

     {  // check EP6 FULL(busy) bit in EP2468STAT (SFR),

        // core set's this bit when FIFO is full

       IOB = EP2FIFOBUF[0];//write PORTB (1byte)　EP2の１バイトをPORTBへ

       EP6FIFOBUF[0] = IOA;//read PORTA (1byte)　PORTAから１バイトEP6へ

       send_count = 1;//1 byte　送信バイト数

       EP6BCH = 0;　EP6書き込みバイト数　上位

       SYNCDELAY;　E600-E6FFの間のレジスタはｒｅａｄ／ｗｒｉｔｅに待ちが必要

       EP6BCL = send_count;//send count , EP6IN　EP6書き込みバイト数　下位

       SYNCDELAY;

       EP2BCL = 0x80;//re-arm EP2OUT　ＥＰ２クリア

       SYNCDELAY;

     }

  }

  if(!(EP2468STAT & bmEP4EMPTY))　EP4が空でないとき（ホストからデータ有り）

  { // check EP4 EMPTY(busy) bit in EP2468STAT (SFR),

    // core set's this bit when FIFO is empty

      EP4BCL = 0x80;          // re-arm EP4OUT　ＥＰ４クリア

  }

}